High Level Synthesis Of Embedded Systems Targeting Reconfigurable Architectures

In this paper, we propose and validate a flow integrating the Unified Modelling Language UML with existing high level synthesis tools targeting reconfigurable architectures. The flow tries to take advantages of UML as a standard for visual object modelling and functional simulation and some CAD tools for profiling, simulation and high level synthesis that work with Xilinx platforms. In order to validate our proposed flow, a case study on the H264 decoder is illustrated.