A Real-time Simulation Platform For The H.264 Codec Modules

In this paper, we propose a real-time platform for H.264 CODEC with a memory management method in which we use a preloading mechanism in order to reduce external memory accessing. The simulation platform uses then an external DDR2 memory to record the images of the sequence and an intelligent memory controller which reads the DDR2 periodically to charge another local memory for the processing modules of the H.264 encoder containing macroblocks (of different size). We either use image manipulation or chosen mode. The proposed intelligent controller is tested on an Xilinx-virtex5-ML501 platform with multiple internal and external components, including a DDR2 of 256MB. Similarly, the proposed memory controller unit is well-adapted to future memory-bandwidth-constraint System-on-Chip applications.